The present invention relates generally to sample rate converters, and more particularly to asynchronous sample rate converters and methods.
The digital audio format has become more and more popular for use in most audio signal applications, especially in applications for audio recording studios. In audio recording studios, various analog audio sources often are sampled at various different sample frequencies and then are digitized to produce various digital audio signals. In the digital format, the audio signals can be edited, reproduced and processed easily without introducing nearly as much distortion and noise as would be introduced if the same the same editing, reproducing and processing were to be performed on the same audio signals in analog format.
However, sample rate converters are necessary for interfacing between devices receiving and/or producing digital signals having different sample rates in order to avoid audio sample dropping or sample repeating, which results in highly undesirable audible “popping” or “clicking” sounds. Even for two devices that receive and/or produce digital signals having the same nominal sample rates but which are based on asynchronous clocks, it is necessary to use an asynchronous sample rate converter to accomplish interfacing between the two devices in order to avoid audio sample dropping or repeating.
There are two well-known kinds of sample rate converters: synchronous sample rate converters and asynchronous sample rate converters. In synchronous sample rate converters, an input sample rate is related to an output sample rate by a ratio of integers. This means that the sample rate of the output signal is locked to, i.e., is synchronized with, the sample rate of the input signal. However, in asynchronous sample rate converters it is not necessary that the sample rate of the output signal be synchronized with the sample rate of the input signal. Asynchronous sample rate converters each receive a stream of input samples, process them and produce output samples when requested, and can be used to convert between any two sample rates irrespective of whether the ratio of the two sample rates is an integer or is a rational number, and irrespective of whether the two sample rates are synchronized.
Because of this feature, an asynchronous sample rate converter can decouple a first digital audio device producing a digital output having a first sample rate and a second digital audio device which is intended to receive the output of the first digital audio device and sampling it at a second sample rate. For example, the sample rate of an audio source device might be 48 kHz, and the desire and d sample rate for an audio destination device might also be 48 kHz, but the clock signals of the audio source device and the audio destination device might be independent and therefore asynchronous. Then, even though the nominal sample rates both are 48 kHz, a very small drift or difference between the frequencies of the above-mentioned clock signals will accumulate and cause the above-mentioned undesirable/annoying sample dropping or sample repeating if a synchronous sample rate converter is used.
However, if an asynchronous sample rate converter is placed between the output of the audio source device and the input of the audio destination device, this effectively decouples them and avoids the effects of the inevitable relative drift between the frequencies of the two independent 48 kHz clock signals. Because of this advantage and the availability of more digital audio sources, the market demand for asynchronous sample rate converters is growing rapidly.
One prior asynchronous sample rate converter, marketed by Cirrus Logic, Inc., by design does not have phase matching. (The term “phase matching” means that multiple asynchronous sample rate converters operating in parallel introduce the same or almost the same delay with respect to their input signals.) Furthermore, the Cirrus Logic asynchronous sample rate converter requires two phase locked loop circuits (either on or off chip), one related to the input sample rate and the other related to the output sample rate. Since a phase locked loop is an analog circuit, the performance of the sample rate converter is affected by temperature, power supply voltage, and integrated circuit manufacturing process being utilized. Furthermore, use of analog phase locked loop circuits usually requires substantially more silicon chip area than would be required if digital techniques were used instead for the same purpose. Also, Cirrus Logic's sample rate converter has its decimation filter turned on all of the time. This has the disadvantage that the overall group delay of the asynchronous sample rate converter is greater than necessary in cases in which there is no aliasing for down-sampling.
Another prior asynchronous sample rate converter marketed by Analog Devices Inc. has only one stage for interpolation, which makes it difficult to achieve large attenuation of images with a reasonable filter length. In the Analog Devices asynchronous sample rate converter, the interpolation filter is very long, and has at least 4,194,304 taps to provide 125 dB attenuation. The amount of attenuation directly affects the total harmonic distortion plus noise (THD+N) performance of the asynchronous sample rate converter. The single stage interpolation filter interpolates the input samples by a ratio of up to 216, resulting in the unreasonably long FIR lowpass filter mentioned above.
When the output sample rate is less than the input sample rate, the interpolation filter coefficients have to be interpolated by the ratio of the output sample rate to the input sample rate to make the passband of the interpolation filter narrower to avoid aliasing. Consequently, the interpolation filter length and coefficients have to be recalculated based on the ratio whenever the input sample rate or output sample rate changes. This may cause a substantial of amount of phase mismatch for multiple parallel-running asynchronous sample rate converters even when they are put into a matched phase mode wherein one asynchronous sample rate converter is set as a master and the rest are set as slaves. The master has to send the phase information to its slaves through an audio serial interface. The Analog Devices asynchronous sample rate converters must be put into a master/slave arrangement and phase information has to be transferred from the master devices to the slave devices in order to achieve matched phase. How well the phase match is accomplished depends on how much information is transferred, and the bandwidth of the audio serial interface may limit the amount of information that can be transferred by the Analog Devices asynchronous sample rate converters.
Thus, there is an unmet need for an asynchronous sample rate converter and method that provides precise phase matching, avoids use of phase locked loop circuits the input sample rate and the output sample rate, provides adequate attenuation of images, avoids the need to have its anti-aliasing filter always turned on, provides improved THD+N performance, and/or avoids the need to recalculate the interpolation filter length whenever the input or output sample rate changes.